ISMVL 2018
IEEE International Symposium
on Multiple-Valued Logic

Program

Tuesday, May 15, 2018
Workshop on Post-Binary ULSI Systems
18:00 Welcome Reception
 
Wednesday, May 16, 2018
8:00-9:00 Registration
9:00-9:15 Opening
9:15-10:00 [Keynote Address I]
Instantaneous and Near-Instantaneous Learning Network
Subhash Kak (Oklahoma State University, Stillwater)
10:00-10:30 Coffee Break
10:30-12:00 [1A. Quaternary Logic]
Chair: M. Miller		 [1B. Multiple-valued Logic Applications]
Chair: T. Sasao
Quaternary Generalized Boolean Bent Functions Obtained Through Permutation of Binary Boolean Bent Functions
Radomir Stankovic, Milena Stankovic, Jaakko Astola and Claudio Moraga		 Application of Multiple-Valued Logic in Importance Analysis of k-out-of-n Multi-State Systems
Jozef Kostolny, Elena Zaitseva, Patrik Rusnak and Miroslav Kvassay
Quaternary Debiasing for Physically Unclonable Functions
Manami Suzuki, Rei Ueno, Naofumi Homma and Takafumi Aoki 		A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor
Haruyoshi Yonekawa, Shimpei Sato and Hiroki Nakahara
Characterization of Quaternary Threshold Functions in the Vilenkin-Chrestenson Basis
Ivan Prokic		 A Reconfigurable Arbiter PUF with 4 x 4 Switch Blocks
Elena Dubrova
12:00-13:30 Lunch (Symposium Committee Meeting)
13:30-15:00 [2A. Multiple-Valued Functions]
Chair: H. Nakahara		 [2B. Security and More]
Chair: E. Dubrova
Beyond Bits: A Quaternary FPGA Architecture using Multi-VT Multi-Vdd FDSOI Devices
Sumanta Chaudhuri		 Systematic Intrusion Detection Technique for In-Vehicle Network Based on Time-Series Feature Extraction
Hiroki Suda, Masanori Natsui and Takahiro Hanyu
An Energy-Efficient Quaternary Serial Adder for Nanoelectronics
Shima Sedighiani and Arman Kazemi 		On the Detectability of Hardware Trojans Embedded in Parallel Multipliers
Akira Ito, Rei Ueno, Naofumi Homma and Takafumi Aoki
On a Memory-Based Realization of Sparse Multiple-Valued Functions
Tsutomu Sasao		 Mining Latency Guarantees for RTL Designs
Jan Malburg, Heinz Riener and Goerschwin Fey
15:00-15:30 Coffee Break
15:30-17:30 [3A. Algebra and Theory]
Chair: N. Homma		 [3B. Reversible Circuits]
Chair: M. Thorton
Track-Down Operations on Bilattices
Damian Szmuc		 Synthesis of Reversible Circuits Using Conventional Hardware Description Languages
Zaid Al-Wardi, Robert Wille and Rolf Drechsler
One Class of Maximal Binary Monomials
Hajime Machida and Jovanka Vanja Pantovic		 Reversible Circuit Optimization based on Tabu Search
Alexandre A. A. De Almeida, Gerhard W. Dueck and Alexandre Cesar Rodrigues Da Silva
Commutation for Functions of Small Arity over a Finite Set
Hajime Machida and Ivo Rosenberg		 Ternary/MV Reversible Functions with Component Functions from Different Equivalence Classes
Pawel Kerntopf, Radomir Stankovic, Krzysztof Podlaski and Claudio Moraga
A representation theorem for quantale valued sup-algebras
Jan Paseka and Radek Slesinger		 Generalizing the Concept of Scalable Reversible Circuit Synthesis for Multiple-valued Logic
Alwin Zulehner, P. Mercy Nesa Rani, Kamalika Datta, Indranil Sengupta and Robert Wille
 
Thursday, May 17, 2018
9:15-10:00 [Keynote Address II]
From Binary to Ternary and Fuzzy Logic in Molecular and Nanoscale Systems
Konrad Szacilowski (AGH University of Science and Technology, Krakow)
10:00-10:30 Coffee Break
10:30-12:00 [4A. New Technologies and Applications]
Chair: R. Stankovic		 [4B. Index Functions and Algebra]
Chair: C. Moraga
Logic Design using Memristors: An Emerging Technology (Tutorial)
Saeideh Shirinzadeh, Kamalika Datta and Rolf Drechsler		 An Exact Method to Enumerate Decomposition Charts for Index Generation Functions
Jon Butler and Tsutomu Sasao
Amoeba-inspired electronic solution-searching system and its application to finding walking maneuver of a multi-legged robot
Kenta Saito, Naoki Suefuji, Seiya Kasai and Masashi Aono 		An Exact Optimization Method Using ZDDs for Linear Decoposition of Index Generation Functions
Shinobu Nagayama, Tsutomu Sasao and Jon Butler
Specific Health Examination Data Prediction for Female Subjects with Unhealthy-Level Visceral Fat Using Self-Organizing Maps
Naotake Kamiura, Takayuki Yumoto and Teijiro Isokawa		 Saturated Models in Mathematical Fuzzy Logic
Guillermo Badia and Carles Noguera
12:00-13:30 Lunch
13:30-22:00 Excursion and Banquet
 
Friday, May 18, 2018
9:15-10:00 [Keynote Address III]
Bent Functions: Results and Applications to Cryptography
Natalia Tokareva (Novosibirsk State University, Novosibirsk)
10:00-10:30 Coffee Break
10:30-12:00 [5A. Design of Multiple-Valued Circuits I]
Chair: Y. Yuminaka		 [5B. Neural Networks Implementation and Applications]
Chair: M. Perkowski
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter
Shogo Mukaida, Naoya Onizawa and Takahiro Hanyu 		An analog-to-digital converter using delta-sigma modulator network
Takao Waho
Multiple-Valued Random Digit Extraction
Micah Thornton and Mitch Thornton		 Efficient Hardware Realization of Convolutional Neural Networks using Intra-Kernel Regular Pruning
Maurice Yang, Mahmoud Faraj, Assem Hussein and Vincent Gaudet
Generating Synthetic MVL Benchmarks from Random MDDs under Restrictions
Milos Radmanovic and Radomir Stankovic		 CNOT-Measure Quantum Neural Networks
Martin Lukac, Kamila Abdiyeva and Michitaka Kameyama
12:00-13:30 Lunch (Technical Committee Meeting)
13:30-15:00 [6A. Design of Multiple-Valued Circuits II ]
Chair: G. Dueck		 [6B. Circuits and Signals]
Chair: N. Onizawa
Design Methodologies for Ternary Logic Circuits
Chetan Vudadha and Srinivas Mandalika		 Multi-Valued Signal Generation and Measurement for PAM-4 Serial Link Test
Natsuki Sato, Takahito Chigira, Kohei Toyoda, Yosuke Iijima and Yasushi Yuminaka
A Spectral Algorithm for Ternary Function Classification
Michael Miller and Mathias Soeken		 Realization of Arithmetic Operators based on Stochastic Number Frequency Signal Representation
Mohammad M.A. Taha and Marek Perkowski
Synthesis of Multi-Valued Literal using Lukasiewicz logic
Anmol Prakash Surhonne, Debjyoti Bhattacharjee and Anupam Chattopadhyay		 Algebra of transient states of Postan signals
Maciej Rudziecki
15:00-15:30 Coffee Break
15:30-17:00 [7A. Reed-Muller and Spectral]
Chair: J. Butler		 [7B. Quantum]
Chair: Lukac
On the number of fixed points of the Reed-Muller-Fourier transform
Tamas Waldhauser		 Multi-Valued Quantum Cascade Realization With Group Decomposition
Michael Saraivanov and Marek Perkowski
Generation of Ternary Bent Functions by Spectral Invariant Operations in the Generalized Reed-Muller Domain
Milena Stankovic, Claudio Moraga and Radomir Stankovic		 Translating between the roots of identity in quantum circuits
Wouter Castryck, Jeroen Demeyer, Alexis De Vos, Oliver Keszocze and Mathias Soeken
On the Reed-Muller-Fourier Spectrum of Multiple-valued Rotation Symmetric Functions
Claudio Moraga, Radomir Stankovic and Jaakko Astola		 A Radix-4 Chrestenson Gate for Optical Quantum Computation
Kaitlin Smith, Tim LaFave Jr., Duncan MacFarlane and Mitchell Thornton
17:00 Plenary Session & Closing