Contact

Johannes Kepler University Linz
Integrated Circuit and System Design
Univ.-Prof. Dr. Robert Wille
Altenberger Straße 69 | SCP3 0405
4040 Linz | Austria
robert.wille@jku.at
Tel: +43 732 2468 4739

Map and directions to JKU

DI Alwin Zulehner

DI Alwin Zulehner
PhD Student

Science Park 3, 3rd floor, room 0319
Phone: +43 732 2468 4570
azulehner@ica.jku.at

Personal Data
Name:Alwin Zulehner
Nationality:Austrian


Education
09/2004-05/2008High School, Traun, Austria
10/2009-09/2012Bachelor's Degree in Computer Science, Johannes Kepler University Linz, Austria
Bachelor’s Thesis: "RAU - A Rational Arithmetic Unit"
10/2012-07/2015Master's Degree in Computer Science, Johannes Kepler University Linz, Austria
Master’s Thesis: "Interpretation of Dynamic Languages in Hardware"

Journals

  1. A. Zulehner, A. Paler, and R. Wille. An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2018. PDF
  2. A. Zulehner and R. Wille. Advanced Simulation of Quantum Computations. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2018. PDF
  3. X. Cui, S. M. Saeed, A. Zulehner, R. Wille, K. Wu, R. Drechsler, and R. Karri. On the Difficulty of Inserting Trojans in Reversible Computing Architectures. IEEE Transactions on Emerging Topics in Computing (TETC), 2018. DOI
  4. A. Zulehner and R. Wille. One-pass Design of Reversible Circuits: Combining Embedding and Synthesis for Reversible Logic. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 37(5): 996-1008, 2018. PDF

Conferences

  1. A. Zulehner and R. Wille. Compiling SU(4) Quantum Circuits to IBM QX Architectures. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2019. Acceptance rate: 35%.
  2. A. Zulehner, M. Frank, and R. Wille. Design Automation for Adiabatic Circuits. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2019. Acceptance rate: 35%.
  3. A. Zulehner, K. Datta, I. Sengupta, and R. Wille. A Staircase Structure for Scalable and Efficient Synthesis of Memristor-Aided Logic. In Asia and South Pacific Design Automation Conference (ASPDAC), 2019. Acceptance rate: 35%.
  4. S. M. Saeed, X. Cui, A. Zulehner, R. Wille, R. Drechsler, K. Wu, and R. Karri. IC/IP Piracy Assessment of Reversible Logic. In International Conference on Computer Aided Design (ICCAD), 2018. Acceptance rate: 25%.
  5. A. Zulehner and R. Wille. QMDD-based One-pass-design of Reversible Logic: Exploring the Available Degree of Freedom. In Conference on Reversible Computation, 2018. PDF
  6. A. Zulehner, P. M. N. Rani, K. Datta, I. Sengupta, and R. Wille. Generalizing the Concept of Scalable Reversible Circuit Synthesis for Multiple-valued Logic. In International Symposium on Multiple-Valued Logic (ISMVL), 115-120, 2018. PDF
  7. R. Wille, P. Niemann, A. Zulehner, and R. Drechsler. Decision Diagrams for the Design of Reversible and Quantum Circuits. In International Symposium on Devices, Circuits and Systems (ISDCS), 2018. Invited Paper. PDF
  8. A. Zulehner, A. Paler, and R. Wille. Efficient Mapping of Quantum Circuits to the IBM QX Architecture. In Design, Automation and Test in Europe (DATE), 1135-1138, 2018. Acceptance rate: 35%. PDF (see also full version at arXiv and implementation at this page).
  9. A. Zulehner and R. Wille. Pushing the Number of Qubits Below the Minimum: Realizing Compact Boolean Components for Quantum Logic. In Design, Automation and Test in Europe (DATE), 1179-1182, 2018. Acceptance rate: 35%. PDF
  10. A. Zulehner and R. Wille. Exploiting Coding Techniques for Logic Synthesis of Reversible Circuits. In Asia and South Pacific Design Automation Conference (ASP-DAC), 670-675, 2018. Acceptance rate: 32%. PDF
  11. S. M. Saeed, N. Mahendran, A. Zulehner, R. Wille, and R. Karri. Identifying Synthesis Approaches for IP Piracy of Reversible Circuits. In International Conference on Computer Design (ICCD), 2017. PDF
  12. A. Zulehner and R. Wille. Improving Synthesis of Reversible Circuits: Exploiting Redundancies in Paths and Nodes of QMDDs. In Conference on Reversible Computation, 232-247, 2017. PDF
  13. A. Zulehner, S. Gasser, and R. Wille. Exact Global Reordering for Nearest Neighbor Quantum Circuits Using A*. In Conference on Reversible Computation, 185-201, 2017. PDF
  14. P. Niemann, A. Zulehner, R. Wille, and R. Drechsler. Efficient Construction of QMDDs for Irreversible, Reversible, and Quantum Functions. In Conference on Reversible Computation, 214-231, 2017. PDF
  15. A. Zulehner and R. Wille. Skipping Embedding in the Design of Reversible Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), 173,178, 2017. PDF
  16. A. Zulehner and R. Wille. Taking One-to-one Mappings for Granted: Advanced Logic Design of Encoder Circuits. In Design, Automation and Test in Europe (DATE), 818-823, 2017. Acceptance rate: 24%. PDF
  17. A. Zulehner and R. Wille. Make It Reversible: Efficient Embedding of Non-reversible Functions. In Design, Automation and Test in Europe (DATE), 458-463, 2017. Acceptance rate: 24%. PDF