Contact

Johannes Kepler University Linz
Integrated Circuit and System Design
Univ.-Prof. Dr. Robert Wille
Altenberger Straße 69 | SCP3 0405
4040 Linz | Austria
robert.wille@jku.at
Tel: +43 732 2468 4739

Map and directions to JKU

Publications

Books

  1. A. Grimmer and R. Wille. Designing Droplet Microfluidic Networks: A Toolbox for Designers. Springer, 2020.
  2. O. Keszocze, R. Wille, and R. Drechsler. Exact Design of Digital Microflluidic Biochips. Springer, 2019.
  3. N. Przigoda, R. Wille, J. Przigoda, and R. Drechsler. Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers. Springer, 2018.
  4. P. Niemann and R. Wille. Compact Representations for the Design of Quantum Logic. Springer, 2017.
  5. J. Seiter, R. Wille, and R. Drechsler. Automatic Methods for the Refinement of System Models. Springer, 2017. DOI
  6. R. Wille and R. Drechsler. Towards a Design Flow for Reversible Logic. Springer, 2010.

Book Chapters

  1. A. Bhattacharjee, C. Bandyopadhyay, B. Mondal, R. Wille, R. Drechsler, and H. Rahaman. An Efficient Nearest Neighbor Design for 2D Quantum Circuits. In A. Singh, M. Fujita, and A. Mohan, editors, Design and Testing of Reversible Logic. Springer, 2020.
  2. S. Poddar, R. Wille, H. Rahaman, and B. B. Bhattacharya. Effect of Volumetric Split-Errors on Reactant-Concentration During Sample Preparation with Microfluidic Biochips. In R. Chaki, A. Cortesi, K. Saeed, and N. Chaki, editors, Advanced Computing and Systems for Security. Springer, 2020.
  3. R. Wille, K. Chakrabarty, R. Drechsler, and P. Kalla. Emerging Circuit Technologies: An Overview on the Next Generation of Circuits. In A. Reis and R. Drechsler, editors, Advanced Logic Synthesis, pages 43-67. Springer, 2018. DOI
  4. O. Keszocze and R. Wille. Exploiting Electronic Design Automation for Checking Legal Regulations: A Vision. In F. Oppenheimer and J. L. Medina Pasaje, editors, Languages, Design Methods, and Tools for Electronic System Design, pages 101-112. Springer, 2016. DOI
  5. R. Wille. Basics, Applications, and Design of Reversible Circuits. In Tomasz Wojcicki, editor, VLSI: Circuits for Emerging Applications, Devices, Circuits, and Systems, pages 261-273. CRC Press, 2014.
  6. R. Drechsler, M. Soeken, and R. Wille. Formal Specification Level. In Jan Haase, editor, Models, Methods, and Tools for Complex Chip Design: Selected Contributions from FDL 2012, pages 37-52. Springer, 2014.
  7. R. Wille, S. Offermann, and R. Drechsler. SyReC: A Programming Language for Synthesis of Reversible Circuits. In T. J. Kazmierski and A. Morawiec, editors, System Specification and Design Languages: Selected Contributions from FDL 2010, pages 207-222. Springer, 2012.
  8. R. Wille, D. Große, F. Haedicke, and R. Drechsler. SMT-based Stimuli Generation in the SystemC Verification Library. In Dominique Borrione, editor, Advances in Design Methods from Modeling Languages for Embedded Systems and SoCs: Selected Contributions on Specification, Design, and Verification from FDL 2009, pages 227-244. Springer, 2010.
  9. R. Wille. Ein Entwurfsablauf für Reversible Schaltkreise. In S. Hölldobler et al., editor, Ausgezeichnete Informatikdissertationen 2009, pages 291-300. GI, 2010.
  10. R. Wille and R. Drechsler. Synthesis of Boolean Functions in Reversible Logic. In T. Sasao, J. T. Butler, and M. Thornton, editors, Progress in Applications of Boolean Functions (Synthesis Lectures on Digital Circuits and Systems), pages 75-92. Morgan and Claypool Publishers, 2010.
  11. D. Große, R. Wille, R. Siegmund, and R. Drechsler. Debugging Contradictory Constraints in Constraint-based Random Simulation. In M. Radetzki, editor, Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL’08, pages 273-290. Springer, 2009.
  12. R. Wille, G. Fey, D. Große, S. Eggersglüß, and R. Drechsler. SWORD: A SAT like Prover Using Word Level Information. In R. Reis, V. Mooney, and P. Hasler, editors, VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip, pages 175-192. Springer, 2009.

Edited Publications

  1. F. Fummi and R. Wille, editors. Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2016, Lecture Notes in Electrical Engineering. Springer, 2018.
  2. S. Yamashita, T.-Y. Ho, R. Wille, and K. Chakrabarty, editors. Microfluidic Biochips: Bridging Biochemistry with Computer Science and Engineering (NII Shonan Meeting No. 2017-1), NII Shonan Meeting Report, 2017.
  3. R. Drechsler and R. Wille, editors. Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2015, Lecture Notes in Electrical Engineering. Springer, 2016. DOI
  4. V. C. Gaudet, J. T. Butler, R. Wille, and N. Homma. Special Issue on Emerging Topics in Multiple-Valued Logic and Its Applications. Journal of Emerging and Selected Topics in Circuits and Systems (JETCAS), 6(1):1-4, 2016. DOI
  5. R. Wille and R. Drechsler. Special Issue of the 44th IEEE International Symposium on Multiple-Valued Logic. Multiple-Valued Logic and Soft Computing, 26(1-2), 2016.
  6. K. Chakrabarty, T.-Y. Ho, and R. Wille, editors. Design of Microfluidic Biochips (Dagstuhl Seminar 15352), Dagstuhl Reports, 2015.
  7. R. Wille, O. Keszocze, and R. Drechsler, editors. Synthese- und Optimierungsverfahren für zukünftige Computerparadigmen. Shaker, 2015.
  8. R. Wille, R. Drechsler, and M. B. Tahoori, editors. Special Issue on Reversible Computation, Journal on Emerging Technologies in Computing Systems (JETC), 2014.
  9. R. Drechsler, M. Soeken, and R. Wille, editors. Auf dem Weg zum Quantencomputer - Entwurf reversibler Logik. Shaker, 2012.
  10. A. DeVos and R. Wille, editors. Reversible Computation 2011, Lecture Notes in Computer Science, 2012.
  11. K. Morita and R. Wille, editors. Design of Reversible and Quantum Circuits (Dagstuhl Seminar 11502), Dagstuhl Reports, 2012.
  12. R. Drechsler, I. Ulidowski, and R. Wille, editors. Special Issue on Reversible Computation, Multiple-Valued Logic and Soft Computing, 2012.

Tutorials

  1. R. Wille, J. Madsen, U. Schlichtmann, and T.-M. Tseng. Design Tools for Microfluidic Devices. In Conference on Miniaturized Systems for Chemistry and Life Sciences (MicroTAS), 2019.
  2. S. Gosh, A. Chattopadhyay, M. Soeken, and R. Wille. QUEST: Quantum computing - EDA, Security and Test. In Design Automation Conference (DAC), 2019.
  3. W. Haselmayr, M. Hamidovic, and R. Wille. Microfluidics Research at JKU. In Workshop on Molecular Communications, 2019.
  4. R. Wille, R. Van Meter, and Y. Naveh. IBM’s Qiskit Tool Chain: Working with and Developing for Real Quantum Computers. In Design, Automation and Test in Europe (DATE), 2019. PDF
  5. R. Wille, A. Fowler, and Y. Naveh. Computer-Aided Design for Quantum Computation. In International Conference on Computer Aided Design (ICCAD), 2018. PDF
  6. R. Wille, B. Li, R. Drechsler, and U. Schlichtmann. Automatic Design of Microfluidic Devices: An Overview of Platforms and Corresponding Design Tasks. In Forum on Specification and Design Languages (FDL), 2018. PDF
  7. W. Haselmayr, R. Wille, and A. Grimmer. Networked Labs-on-Chips (NLoCs): A Passive Droplet Routing Concept for Two-Phase Flow Microfluidics. In Conference on Miniaturized Systems for Chemistry and Life Sciences (MicroTAS), 2017.
  8. R. Wille and B. Li. Design Automation for Labs-on-Chip: A New Playground for SoC Designers. In International System-on-Chip Conference (SOCC), 2017.
  9. R. Wille, B. Li, U. Schlichtmann, and R. Drechsler. From Biochips to Quantum Circuits: Computer-Aided Design for Emerging Technologies. In International Conference on Computer Aided Design (ICCAD), 2016. PDF
  10. R. Wille, K. Chakrabarty, P. Kalla, and R Drechsler. Emerging Technologies. In International Workshop on Logic Synthesis (IWLS), 2016.
  11. M. Alistar, K. Chakrabarty, J. Madsen, T.-Y. Ho, and R. Wille. When Embedded Systems meet Life Sciences: Microfluidic Biochips for Real-Time Healthcare. In Embedded Systems Week (ESWEEK), 2016.
  12. R. Wille. Reversible Circuits: Design Methods for an Emerging Technology. In IEEE International Symposium on Circuits and Systems, 2016.
  13. R. Wille and R. Drechsler. Formal Methods for Emerging Technologies. In International Conference on Computer Aided Design (ICCAD), 2015. PDF
  14. U. Schlichtmann, P. Pop, R. Wille, and B. Li. Microfluidics Meets Electronic Design Automation. In Zuverlässigkeit und Entwurf (ZuE), 2015.
  15. R. Drechsler and R. Wille. Formal Methods for Emerging Technologies. In International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2015.
  16. R. Drechsler, M. Soeken, and R. Wille. Automated and Quality-driven Requirements Engineering. In International Conference on Computer Aided Design (ICCAD), 2014. PDF
  17. K. Datta, R. Wille, I. Sengupta, and H. Rahaman. Reversible Circuits - Design Methods for an Emerging Technology. In International Symposium on VLSI Design and Test (VDAT), 2014.
  18. R. Drechsler, R. Findenig, and R. Wille. The Formal Specification Level: Bridging the Gap between the Spec and its Implementation. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2014.
  19. R. Drechsler, M. Soeken, and R. Wille. Text statt C++: Automatisierung des Systementwurfs mit Hilfe natürlicher Sprachverarbeitung. In INFORMATIK 2013 - 43. Jahrestagung der Gesellschaft für Informatik, 2013.
  20. R. Wille. Reversible Computation. In International Symposium on Electronic System Design (ISED), 2012.
  21. R. Drechsler, R. Findenig, I. Harris, R. Wille, and W. Ecker. Design and Verification of Embedded Systems from Natural Language Descriptions. In Design, Automation and Test in Europe (DATE), 2013.
  22. R. Wille. Reversible Computation. In International Symposium on Electronic System Design (ISED), 2012.
  23. R. Drechsler, I. Harris, and R. Wille. Generating Formal System Models from Natural Language Descriptions. In International High Level Design Validation and Test Workshop (HLDVT), 2012.

Journals

  1. P. Roy, A. Banerjee, R. Wille, and B. B. Bhattacharya. Harnessing the Granularity of Micro-Electrode-Dot-Array Architectures for optimizing Droplet Routing in Biochips. Transactions on Design Automation of Electronic Systems (TODAES), 2019.
  2. F. Sill Torres, P. Niemann, R. Wille, and R. Drechsler. Near Zero-Energy Computation Using Quantum-dot Cellular Automata. Journal on Emerging Technologies in Computing Systems (JETC), 2019. PDF
  3. Y. Zhu, X. Huang, B. Li, T.-Y. Ho, Q. Wang, H. Yao, R. Wille, and U. Schlichtmann. MultiControl: Advanced Control Logic Synthesis for Flow-Based Microfluidic Biochips. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2019. PDF
  4. L. Servadei, E. Zennaro, T. Fritz, K. Devarajegowda, W. Ecker, and R. Wille. Using Machine Learning for Predicting Area and Firmware Metrics of Hardware Designs from Abstract Specifications. Microprocessors and Microsystems (MICPRO), 2019.
  5. S. Saeed, A. Zulehner, R. Wille, R. Drechsler, and R. Karri. Reversible Circuits: IC/IP Piracy Attacks and Countermeasures. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2019. PDF
  6. S. Bhattacharjee, R. Wille J.-D. Huang, and B. B. Bhattacharya. Storage-Aware Algorithms for Dilution and Mixture Preparation with Flow-Based Lab-on-Chip. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2019. PDF
  7. A. Grimmer, M. Hamidovic, W. Haselmayr, and R. Wille. Advanced Simulation of Droplet Microfluidics. Journal on Emerging Technologies in Computing Systems (JETC), 2019. PDF
  8. M. Walter, R. Wille, D. Große, F. Sill Torres, and R. Drechsler. Placement & Routing for Tile-based Field-coupled Nanocomputing Circuits is NP-complete. Journal on Emerging Technologies in Computing Systems (JETC), 2019. PDF
  9. A. Paler, A. Fowler, and R. Wille. Faster manipulation of large quantum circuits using wire label reference diagrams. Microprocessors and Microsystems (MICPRO), 66:55-66, 2019.
  10. F. Angerer, A. Grimmer, H. Prähofer, and P. Grünbacher. Change Impact Analysis for Maintenance and Evolution of Variable Software Systems. Automated Software Engineering, 2019.
  11. M. Hamidovic, W. Haselmayr, A. Grimmer, R. Wille, and A. Springer. Passive droplet control in microfluidic networks: A survey and new perspectives on their practical realization. Nano Communication Networks, 19:33-46, 2019. PDF
  12. A. Grimmer, W. Haselmayr, and R. Wille. Automatic Droplet Sequence Generation for Microfluidic Networks with Passive Droplet Routing. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2018. PDF
  13. S. Huhn, S. Frehse, R. Wille, and R. Drechsler. Determining Application-specific Knowledge for Improving Robustness of Sequential Circuits. IEEE Trans. on VLSI Systems, 2018. PDF
  14. A. Grimmer, P. Frank, P. Ebner, S. Häfner, A. Richter, and R. Wille. Meander Designer: Automatically Generating Meander Channel Designs. Micromachines, 9(12), 2018. PDF
  15. A. Grimmer, X. Chen, M. Hamidovic, W. Haselmayr, C. L. Ren, and R. Wille. Simulation before fabrication: a case study on the utilization of simulators for the design of droplet microfluidic networks. RSC Advances, 8(60):34733-34742, 2018. PDF
  16. S. M. Saeed, N. Mahendran, A. Zulehner, R. Wille, and R. Karri. Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits. Journal on Emerging Technologies in Computing Systems (JETC), 2018. PDF
  17. S. Poddar, R. Wille, H. Rahaman, and B. B. Bhattacharya. Error-Oblivious Sample Preparation With Digital Microfluidic Lab-on-Chip. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2018. PDF
  18. A. Zulehner, A. Paler, and R. Wille. An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2018. PDF
  19. A. Zulehner and R. Wille. Advanced Simulation of Quantum Computations. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2018. PDF
  20. A. Grimmer, W. Haselmayr, and R. Wille. Automated Dimensioning of Networked Labs-on-Chip. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2018. PDF
  21. X. Cui, S. M. Saeed, A. Zulehner, R. Wille, K. Wu, R. Drechsler, and R. Karri. On the Difficulty of Inserting Trojans in Reversible Computing Architectures. IEEE Transactions on Emerging Topics in Computing (TETC), 2018. DOI
  22. F. Sill Torres, R. Wille, P. Niemann, and R. Drechsler. An Energy-aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2018. PDF
  23. N. Przigoda, P. Niemann, J. G. Filho, R. Wille, and R. Drechsler. Frame Conditions in the Automatic Validation and Verification of UML/OCL Models: A Complementary Approach Using modifies only Statements. Computer Languages, Systems & Structures, 56:512-527, 2018.
  24. C. Bandyopadhyaya, R. Dasa, R. Wille, R. Drechsler, and H. Rahaman. Synthesis of Circuits based on All-Optical Mach-Zehnder Interferometers Using Binary Decision Diagrams. Microelectroics Journal, 71(1):19-29, 2018. PDF
  25. A. Grimmer, W. Haselmayr, A. Springer, and R. Wille. Design of Application-Specific Architectures for Networked Labs-on-Chips. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 37(1): 193-202, 2018. PDF
  26. A. Zulehner and R. Wille. One-pass Design of Reversible Circuits: Combining Embedding and Synthesis for Reversible Logic. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 37(5): 996-1008, 2018. PDF
  27. Q. Wang, H. Zou, H. Yao, T.-Y. Ho, R. Wille, and Y. Cai. Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 37(6): 1157-1170, 2018. PDF
  28. A. Paler, A. G. Fowler, and R. Wille. Online scheduled execution of quantum circuits protected by surface codes. Quantum Information & Computation (QIC), 2017. PDF
  29. M. Haghparast, R.Wille, and A. T. Monfared. Towards quantum reversible ternary coded decimal adder. Quantum Information Processing, 7(1), 2017.
  30. A. Paler, A. G. Fowler, and R. Wille. Synthesis of Arbitrary Quantum Circuits to Topological Assembly: Systematic, Online and Compact. Scientific Reports, 7(1), 2017. PDF
  31. R. Wille, O. Keszocze, L. Othmer, M. K. Thomsen, and R. Drechsler. An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs. Journal of Low Power Electronics (JOLPE), 13(4), 2017.
  32. A. Deb, R. Wille, O. Keszocze, S. Shirinzadeh, and R. Drechsler. Synthesis of Optical Circuits Using Binary Decision Diagrams. INTEGRATION, the VLSI Jour., 59:42-51, 2017.
  33. A. Grimmer, J. Clemens, and R. Wille. Formal Methods for Reasoning and Uncertainty Reduction in Evidential Grid Maps. International Journal of Approximate Reasoning (IJA), 87:23-39, 2017. PDF
  34. P. Gonzalez de Aledo, N. Przigoda, R. Wille, R. Drechsler, and P. Sanchez. Towards a Verification Flow Across Abstraction Levels: Verifying Implementations Against Their Formal Specification. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 36(3):475-488, 2017. PDF
  35. N. Przigoda, M. Soeken, R. Wille, and R. Drechsler. Verifying the Structure and Behavior in UML/OCL Models Using Satisfiability Solvers. Cyber-Physical Systems: Theory & Applications, 1(1):49-59, 2016. PDF
  36. D. Rabiser, H. Prähofer, P. Grünbacher, M. Petruzelka, K. Eder, F. Angerer, M. Kromoser, A. Grimmer. Multi-Purpose, Multi-Level Feature Modeling of Large-Scale Industrial Software Systems. Journal on Software and Systems Modeling, 2016.
  37. A. Deb, R. Wille, O. Keszocze, S. Hillmich, and R. Drechsler. Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits. Journal on Emerging Technologies in Computing Systems (JETC), 13(1), 2016. PDF
  38. A. Paler, A. G. Fowler, and R. Wille. Reliable quantum circuits have defects. ACM Crossroads, 23(1):34-38, 2016. PDF
  39. A. Paler, R. Wille, and S. J. Devitt. Wire recycling for quantum circuit optimization. Physical Review A, 94(4), 2016.
  40. M. Soeken, R. Wille, O. Keszocze, D. M. Miller, and Rolf Drechsler. Embedding of Large Boolean Functions for Reversible Logic. Journal on Emerging Technologies in Computing Systems (JETC), 12(4), 2016. PDF
  41. A. Deb, D. K. Das, H. Rahaman, R. Wille, R. Drechsler, and B. B. Bhattacharya. Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. Journal on Emerging Technologies in Computing Systems (JETC), 12(4), 2016. PDF
  42. N. Przigoda, R. Wille, and R. Drechsler. Analyzing Inconsistencies in UML/OCL Models. Journal of Circuits, Systems and Computers, 25(3), 2016. PDF
  43. R. Wille, E. Schonborn, M. Soeken, and R. Drechsler. SyReC: A Hardware Description Language for the Specification and Synthesis of Reversible Circuits. INTEGRATION, the VLSI Jour., 53(3):39-53, 2016. PDF
  44. P. Niemann, R. Wille, D. M. Miller, M. A. Thornton, and R. Drechsler. QMDDs: Efficient Quantum Function Representation and Manipulation. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 35(1):86-99, 2016. PDF
  45. R. Wille, O. Keszocze, T. Boehnisch, A. Kroker, and R. Drechsler. Scalable One-Pass Synthesis for Digital Microfluidic Biochips. IEEE Design & Test, 32(6):41-50, 2015. PDF
  46. R. Wille, A. Lye, and R. Drechsler. Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 33(12):1818-1831, 2014. PDF
  47. R. Wille, M. Soeken, D. M. Miller, and R. Drechsler. Trading Off Circuit Lines and Gate Costs in the Synthesis of Reversible Logic. INTEGRATION, the VLSI Jour., 47(2):284-294, 2014. PDF
  48. R. Wille, A. Lye, and R. Drechsler. Considering Nearest Neighbor Constraints of Quantum Circuits at the Reversible Circuit Level. Quantum Information Processing, 13(2):185-199, 2014. PDF
  49. R. Wille, M. Soeken, N. Przigoda, and R. Drechsler. Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits. Multiple-Valued Logic and Soft Computing, 21(5-6):627-640, 2013.
  50. M. Soeken, S. Frehse, R. Wille, and R. Drechsler. RevKit: An Open Source Toolkit for the Design of Reversible Circuits. Reversible Computation 2011 (Series: Lecture Notes in Computer Science), 7165(1):64-76, 2012. PDF
  51. M. Soeken, S. Frehse, R. Wille, and R. Drechsler. A Toolkit for Reversible Circuit Design. Multiple-Valued Logic and Soft Computing, 18(1):55-65, 2012.
  52. M. Saeedi, R. Wille, and R. Drechsler. Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures. Quantum Information Processing, 10(3):355-377, 2011. PDF
  53. R. Wille, D. Große, S. Frehse, G. W. Dueck, and R. Drechsler. Debugging Reversible Circuits. INTEGRATION, the VLSI Jour., 44(1):51-61, 2011. DOI
  54. R. Wille and R. Drechsler. BDD-Based Synthesis of Reversible Logic. International Journal of Applied Metaheuristic Computing (IJAMC), 1(4):25-41, 2010. Invited Paper.
  55. R. Wille and R. Drechsler. Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic. Electronic Notes in Theoretical Computer Science, 253(6):57-70, 2010. DOI
  56. R. Wille and R. Drechsler. Synthese reversibler Logik. It-Information Technology, 51(1):30-38, 2010. PDF
  57. D. Große, R. Wille, G.W. Dueck, and R. Drechsler. Exact Synthesis of Elementary Quantum Gate Circuits. Multiple-Valued Logic and Soft Computing, 15(4):283-300, 2009.
  58. D. Große, R. Wille, G.W. Dueck, and R. Drechsler. Exact Multiple Control Toffoli Network Synthesis with SAT Techniques. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 28(5):703-715, 2009. DOI
  59. R. Wille, G. Fey, and R. Drechsler. Building Free Binary Decision Diagrams Using SAT Solvers. Facta Universitatis, Series: Electronics and Energetics, 20(3):381-394, 2007.

Conferences

  1. L. Burgholzer and R. Wille. Advanced Equivalence Checking of Quantum Circuits. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2020. Acceptance rate: 34%.
  2. A. Zulehner, S. Hillmich, I. Markov, and R. Wille. Approximation of Quantum States Using Decision Diagrams. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2020. Acceptance rate: 34%.
  3. S. Hillmich, A. Zulehner, and R. Wille. Concurrency in DD-based Quantum Circuit Simulation. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2020. Acceptance rate: 34%.
  4. F. Bornebusch, C. Lüth, R. Wille, and R. Drechsler. Towards Automatic Hardware Synthesis from Formal Specification to Implementation. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2020. Acceptance rate: 34%.
  5. R. Wille, M. Haghparast, S. Adarsh, and T. M. Towards HDL-based Synthesis of Reversible Circuits with No Additional Lines. In International Conference on Computer Aided Design (ICCAD), 2019. Acceptance rate: 25%. PDF
  6. A. Zulehner, S. Hillmich, and R. Wille. How to Efficiently Handle Complex Values? Implementing Decision Diagrams for Quantum Computation. n International Conference on Computer Aided Design (ICCAD), 2019. Acceptance rate: 25%. PDF
  7. M. Hamidovic, U. Marta, H. Bridle, G. Fink, R. Wille, A. Springer, and W. Haselmayr. Simple and Passive Merging-On-Demand Method for Reaction Engineering in Droplet Microfluidics. In International Conference on Miniaturized Systems for Chemistry and Life Sciences (µTAS), 2019. PDF
  8. S. Saeed, R. Wille, and R. Karri. Locking the Design of Building Blocks for Quantum Circuits. In Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2019.
  9. G. Fink, M. Hamidovic, W. Haselmayr, and R. Wille. Towards Design Automation for Microfluidic Devices. In Conference on Micro Fluidic Handling Systems (MFHS), 2019.
  10. M. Hamidovic, U. Marta, G. Fink, R. Wille, A. Springer, and W. Haselmayr. Information Encoding in Droplet-Based Microfluidic Systems: First Practical Study. In International Conference on Nanoscale Computing and Communication (NanoCom), 2019.
  11. S. Pointner and Robert Wille. Did we Test Enough? Functional Coverage for Post-Silicon Validation. In International Test Conference in Asia (ITC-Asia), 2019. PDF
  12. S. Pointner, O. Frank, C. Hazott, and Robert Wille. Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019. PDF
  13. F. Serajeh-Hassani, M. Sadrosadati, S. Pointner, R. Wille, and H. Sarbazi-Azad. Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019. PDF
  14. R. Wille, M. Walter, F. Sill Torres, D. Grosse, and R. Drechsler. Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-coupled Nanotechnologies. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019. PDF
  15. A. Zulehner, H. Bauer, and R. Wille. Evaluating the Flexibility of A* for Mapping Quantum Circuits. In Conference on Reversible Computation, 2019. PDF
  16. R. Wille, L. Burgholzer, and A. Zulehner. Mapping Quantum Circuits to IBM QX Architectures Using the Minimal Number of SWAP and H Operations. In Design Automation Conference (DAC), 2019. Acceptance rate: 25%. PDF
  17. S. Pointner, A. Grimmer, and R. Wille. Exact Stimuli Minimization for Simulation-Based Verification. In IEEE International Symposium on Circuits and Systems, 2019. PDF
  18. A. Zulehner, P. Niemann, R. Drechsler, and R. Wille. One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), 2019. PDF
  19. N. Przigoda, J. Przigoda, and R. Wille. The Four-valued Logic in UML/OCL Models: A New “Playground” for the MVL Community. In International Symposium on Multiple-Valued Logic (ISMVL), 2019. PDF
  20. S. Pointner, P. Gonzalez de Aledo, and R. Wille. Generic Error Localization for the Electronic System Level. In International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2019. PDF
  21. A. Zulehner and R. Wille. Matrix-Vector vs. Matrix-Matrix Multiplication: Potential in DD-based Simulation of Quantum Computations . In Design, Automation and Test in Europe (DATE), 2019. Acceptance rate: 35%. PDF
  22. M. Ring, F. Bornebusch, C. Lüth, R. Wille, and R. Drechsler. Better Late Than Never Verification of Embedded Systems After Deployment. In Design, Automation and Test in Europe (DATE), 2019. Acceptance rate: 35%, Best Paper Award Candidate. PDF
  23. L. Servadei, E. Zennaro, K. Devarajegowda, M. Manzinger, W. Ecker, and R. Wille. Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision. In Design, Automation and Test in Europe (DATE), 2019. Acceptance rate: 35%. PDF
  24. A. Zulehner, P. Niemann, R. Drechsler, and R. Wille. Accuracy and Compactness in Decision Diagrams for Quantum Computation. In Design, Automation and Test in Europe (DATE), 2019. Acceptance rate: 35%. PDF
  25. K. Verma, J. Oder, and R. Wille. Simulating Industrial Electrophoretic Deposition on Distributed Memory Architectures. In Euromicro Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2019. PDF
  26. A. Zulehner and R. Wille. Compiling SU(4) Quantum Circuits to IBM QX Architectures. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2019. Acceptance rate: 35%. PDF
  27. A. Zulehner, M. Frank, and R. Wille. Design Automation for Adiabatic Circuits. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2019. Acceptance rate: 35%. PDF
  28. A. Zulehner, K. Datta, I. Sengupta, and R. Wille. A Staircase Structure for Scalable and Efficient Synthesis of Memristor-Aided Logic. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2019. Acceptance rate: 35%, Best Paper Award Candidate. PDF
  29. Z. Zhong, R. Wille, and K. Chakrabarty. Robust Sample Preparation on Low-Cost Digital Microfluidic Biochips. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2019. Acceptance rate: 35%. PDF
  30. M. Walter, R. Wille, F. Sill Torres, D. Große, and R. Drechsler. Scalable Design for Field-coupled Nanocomputing Circuits. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2019. Acceptance rate: 35%. PDF
  31. A. Bhattacharjee, C. Bandyopadhyay, R. Wille, R. Drechsler, and H. Rahaman. Improved Look-ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits. In International Conference on VLSI Design (VLSI Design), 2019. PDF
  32. M. Hamidovic, W. Haselmayr, A. Grimmer, and R. Wille. Droplet-on-Demand for Realizing Flexible and Programmable Lab-on-chip Devices. In International Conference on Miniaturized Systems for Chemistry and Life Sciences (µTAS), pages 2439-2440, 2018. PDF
  33. Y. Zhu, B. Li, T.-Y. Ho, Q. Wang, H. Yao, R. Wille, and U. Schlichtmann. Multi-Channel and Fault-Tolerant Control Multiplexing for Flow-Based Microfluidic Biochips. In International Conference on Computer Aided Design (ICCAD), 2018. Acceptance rate: 25%. PDF
  34. S. M. Saeed, X. Cui, A. Zulehner, R. Wille, R. Drechsler, K. Wu, and R. Karri. IC/IP Piracy Assessment of Reversible Logic. In International Conference on Computer Aided Design (ICCAD), 2018. Acceptance rate: 25%. PDF
  35. K. Verma, C. Peng, K. Szewc, and R. Wille. A Multi-GPU PCISPH Implementation with Efficient Memory Transfers. In High Performance Extreme Computing Conference (HPEC), 2018. PDF
  36. A. Zulehner and R. Wille. QMDD-based One-pass-design of Reversible Logic: Exploring the Available Degree of Freedom. In Conference on Reversible Computation, 2018. PDF
  37. M. Hamidovic, W. Haselmayr, A. Grimmer, R. Wille, and A. Springer. Comparison of Switching Principles in Microfluidic Bus Networks. In International Conference on Nanoscale Computing and Communication (NanoCom), 2018. PDF
  38. F. Sill Torres, R. Wille, M. Walter, P. Niemann, D. Große, and R. Drechsler. Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata. In Euromicro Conference on Digital System Design (DSD), 2018. PDF
  39. F. Sill Torres, M. Walter, R. Wille, D. Große, and R. Drechsler. Synchronization of Clocked Field-Coupled Circuits. In IEEE International Conference on Nanotechnology (IEEE Nano), 2018. PDF
  40. K. Verma, L. Ayuso, and R. Wille. Parallel Simulation of Electrophoretic Deposition for Industrial Automotive Applications. In International Conference on High Performance Computing & Simulation (HPCS), 2018. PDF
  41. A. Bhattacharjee, C. Bandyopadhyay, R. Wille, R. Drechsler, and H. Rahaman. A Novel Approach for Nearest Neighbor ealization of 2D Quantum Circuits. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 305-310, 2018. PDF
  42. Z. Al-Wardi, R. Wille, and R. Drechsler. Synthesis of Reversible Circuits Using Conventional Hardware Description Languages. In International Symposium on Multiple-Valued Logic (ISMVL), 97-102, 2018. PDF
  43. A. Zulehner, P. M. N. Rani, K. Datta, I. Sengupta, and R. Wille. Generalizing the Concept of Scalable Reversible Circuit Synthesis for Multiple-valued Logic. In International Symposium on Multiple-Valued Logic (ISMVL), 115-120, 2018. PDF
  44. R. Wille, P. Niemann, A. Zulehner, and R. Drechsler. Decision Diagrams for the Design of Reversible and Quantum Circuits. In International Symposium on Devices, Circuits and Systems (ISDCS), 2018. Invited Paper. PDF
  45. M. Walter, R. Wille, D. Grosse, F. Sill Torres, and R. Drechsler. An Exact Method for Design Exploration of Quantum-dot Cellular Automata. In Design, Automation and Test in Europe (DATE), 503-508, 2018. Acceptance rate: 35%. PDF
  46. P. Niemann, R. Wille, and R. Drechsler. Improved Synthesis of Clifford+T Quantum Functionality. In Design, Automation and Test in Europe (DATE), 597-600, 2018. Acceptance rate: 35%. PDF
  47. A. Zulehner, A. Paler, and R. Wille. Efficient Mapping of Quantum Circuits to the IBM QX Architecture. In Design, Automation and Test in Europe (DATE), 1135-1138, 2018. Acceptance rate: 35%. PDF (see also full version at arXiv and implementation at this page).
  48. A. Zulehner and R. Wille. Pushing the Number of Qubits Below the Minimum: Realizing Compact Boolean Components for Quantum Logic. In Design, Automation and Test in Europe (DATE), 1179-1182, 2018. Acceptance rate: 35%. PDF
  49. S. Bhattacharjee, R. Wille, J.-D. Huang, and B. Bhattacharya. Storage-Aware Sample Preparation Using Flow-based Microfluidic Lab-on-Chip. In Design, Automation and Test in Europe (DATE), 1399-1404, 2018. Acceptance rate: 35%. PDF
  50. W. Haselmayr, M. Hamidovic, A. Grimmer, and R. Wille. Fast and Flexible Drug Screening Using a Pure Hydrodynamic Droplet Control. In European Conference on MicroFluidics, 2018. PDF
  51. A. Grimmer, B. Klepic, T.-Y. Ho, and R. Wille. Sound Valve-Control for Programmable Microfluidic Devices. In Asia and South Pacific Design Automation Conference (ASP-DAC), 40-45, 2018. Acceptance rate: 32%. PDF
  52. A. Zulehner and R. Wille. Exploiting Coding Techniques for Logic Synthesis of Reversible Circuits. In Asia and South Pacific Design Automation Conference (ASP-DAC), 670-675, 2018. Acceptance rate: 32%. PDF
  53. P. Niemann, N. Przigoda, R. Wille, and R. Drechsler. Analyzing Frame Conditions in UML/OCL Models: Consistency, Equivalence, and Independence. In Int’l Conf. on Model-Driven Engineering and Software Development (MODELSWARD), 139-151, 2018. PDF
  54. O. Keszocze, M. Ibrahim, R. Wille, K. Chakrabarty, and R. Drechsler. Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips. In International Conference on VLSI Design (VLSI Design), 121-126, 2018. PDF
  55. F. Bornebusch, R. Wille, R. Drechsler. Towards Lightweight Satisfiability Solvers for Self-Verification. In International Symposium on Embedded computing & system Design (ISED), 2017. Invited Paper. PDF
  56. S. M. Saeed, N. Mahendran, A. Zulehner, R. Wille, and R. Karri. Identifying Synthesis Approaches for IP Piracy of Reversible Circuits. In International Conference on Computer Design (ICCD), 2017. PDF
  57. A. Kole, K. Datta, R. Wille, and I. Sengupta. A Nearest Neighbor Quantum Cost Metric for the Reversible Circuit Level. In IEEE Region Ten Conference (TENCON), 2017.
  58. A. Deb, R. Wille, and R. Drechsler. Dedicated Synthesis for MZI-based Optical Circuits based on AND-Inverter Graphs. In International Conference on Computer Aided Design (ICCAD), 2017. Acceptance rate: 24%. PDF
  59. T. van Dijk, R. Wille, and R. Meolic. Tagged BDDs: Combining Reduction Rules from Different Decision Diagram Types. In International Conference on Formal Methods in CAD (FMCAD), 2017. PDF
  60. N. Przigoda, P. Niemann, J. Peters, F. Hilken, R. Wille, and R. Drechsler. More than true or false: Native Support of Irregular Values in the Automatic Validation & Verification of UML/OCL Models. In International Conference on Formal Methods and Models for Codesign (MEMOCODE), 77-86, 2017. PDF
  61. K. Verma, K. Szewc, and R. Wille. Advanced Load Balancing for SPH Simulations on Multi-GPU Architectures. In High Performance Extreme Computing Conference (HPEC), 2017. Best Paper Finalist. PDF
  62. M. Gogolla, F. Hilken, P. Niemann, and R. Wille. Formulating Model Verification Tasks Prover-Independently as UML Diagrams. In European Conference on Modelling Foundations and Applications, 232-247, 2017. PDF
  63. J. Stoppe, O. Keszocze, M. Luenert, R. Wille, and R. Drechsler. BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 170-175, 2017. PDF
  64. A. Zulehner and R. Wille. Improving Synthesis of Reversible Circuits: Exploiting Redundancies in Paths and Nodes of QMDDs. In Conference on Reversible Computation, 232-247, 2017. PDF
  65. A. Zulehner, S. Gasser, and R. Wille. Exact Global Reordering for Nearest Neighbor Quantum Circuits Using A*. In Conference on Reversible Computation, 185-201, 2017. PDF
  66. P. Niemann, A. Zulehner, R. Wille, and R. Drechsler. Efficient Construction of QMDDs for Irreversible, Reversible, and Quantum Functions. In Conference on Reversible Computation, 214-231, 2017. PDF
  67. A. Kole, R. Wille, K. Datta, and I. Sengupta. Test Pattern Generation Effort Evaluation of Reversible Circuits. In Conference on Reversible Computation, 162-175, 2017. PDF
  68. Z. Al-Wardi, R. Wille, and R. Drechsler. Towards VHDL-based Design of Reversible Circuits. In Conference on Reversible Computation, 102-108, 2017. PDF
  69. A. Prakash Surhonne, A. Chattopadhyay, and R. Wille. Automatic Test Pattern Generation for Multiple Missing Gate Faults in Reversible Circuits. In Conference on Reversible Computation, 176-182, 2017. PDF
  70. A. Rauchenecker, T. Ostermann, and R. Wille. Exploiting Reversible Logic Design for Implementing Adiabatic Circuits. In International Conference on Mixed Design of Integrated Circuits and Systems, 264-270, 2017. PDF
  71. A. Grimmer, W. Haselmayr, A. Springer, and R. Wille. A Discrete Model for Networked Labs-on-Chip: Linking the Physical World to Design Automation. In Design Automation Conference (DAC), 50:1-50:6, 2017. Acceptance rate: 24%. PDF
  72. W. Haselmayr, A. Biral, A. Grimmer, A. Zanella, A. Springer, R. Wille. Addressing Multiple Nodes in Networked Labs-on-Chips without Payload Re-injection. In International Conference on Communications (ICC), 1-6, 2017. Acceptance rate: 38%. PDF
  73. A. Rauchenecker and R. Wille. An Efficient Physical Design of Fully-testable BDD-based Circuits. In International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 6-11, 2017. PDF
  74. A. Zulehner and R. Wille. Skipping Embedding in the Design of Reversible Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), 173-178, 2017. PDF
  75. A. Deb, R. Wille, and R. Drechsler. OR-Inverter Graphs for the Synthesis of Optical Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), 278-283, 2017. PDF
  76. Z. Al-Wardi, R. Wille, and R. Drechsler. Extensions to the Reversible Hardware Description Language SyReC. In International Symposium on Multiple-Valued Logic (ISMVL), 185-190, 2017. PDF
  77. A. Grimmer, W. Haselmayr, A. Springer, and R. Wille. Verification of Networked Labs-on-Chip Architectures. In Design, Automation and Test in Europe (DATE), 1679-1684, 2017. Acceptance rate: 24%. PDF
  78. A. Zulehner and R. Wille. Taking One-to-one Mappings for Granted: Advanced Logic Design of Encoder Circuits. In Design, Automation and Test in Europe (DATE), 818-823, 2017. Acceptance rate: 24%. PDF
  79. A. Zulehner and R. Wille. Make It Reversible: Efficient Embedding of Non-reversible Functions. In Design, Automation and Test in Europe (DATE), 458-463, 2017. Acceptance rate: 24%. PDF
  80. W. Haselmayr, A. Grimmer, and R. Wille. Stochastic Computing Using Droplet-Based Microfluidics. In International Conference on Computer Aided Systems Theory (EUROCAST), 2017. PDF
  81. A. Grimmer, Q. Wang, H. Yao, T.-Y. Ho, and R. Wille. Close-to-Optimal Placement and Routing for Continuous-Flow Microfluidic Biochips. In Asia and South Pacific Design Automation Conference (ASP-DAC), 530-535, 2017. Acceptance rate: 31%. PDF
  82. O. Keszocze, Z. Li, A. Grimmer, R. Wille, K. Chakrabarty, and R. Drechsler. Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips. In Asia and South Pacific Design Automation Conference (ASP-DAC), 708-713, 2017. Acceptance rate: 31%. PDF
  83. S. Huhn, S. Frehse, R. Wille, and R. Drechsler. Enhancing Robustness of Sequential Circuits Using Application-specific Knowledge and Formal Methods. In Asia and South Pacific Design Automation Conference (ASP-DAC), 182-187, 2017. Acceptance rate: 31%. PDF
  84. R. Wille, O. Keszocze, L. Othmer, M. K. Thomsen, and R. Drechsler. Generating and Checking Control Logic in the HDL-based Design of Reversible Circuits. In International Symposium on Electronic System Design (ISED), 2016. PDF
  85. S. Burman, K. Datta, R. Wille, I. Sengupta, and R. Drechsler. An Improved Gate Library for Logic Synthesis of Optical Circuits. In International Symposium on Electronic System Design (ISED), 2016. PDF
  86. J. G. Filho, N. Przigoda, R. Wille, and R. Drechsler. Towards a Model-Based Verification Methodology for Complex Swarm Systems. In International Symposium on Electronic System Design (ISED), 2016. Invited Paper. PDF
  87. J. Peters, N. Przigoda, R. Wille, and R. Drechsler. Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models. In International Conference on Formal Methods and Models for Codesign (MEMOCODE), 2016. Acceptance rate: 26%. PDF
  88. N. Przigoda, J. G. Filho, P. Niemann, R. Wille, and R. Drechsler. Frame Conditions in Symbolic Representations of UML/OCL Models. In International Conference on Formal Methods and Models for Codesign (MEMOCODE), 2016. Acceptance rate: 26%. PDF
  89. N. Przigoda, R. Wille, and R. Drechsler. Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding. In International Conference on Model Driven Engineering Languages and Systems (MODELS), 2016. Acceptance rate: 24%. PDF
  90. R. Wille, A. Chattopadhyay, and R. Drechsler. From Reversible Logic to Quantum Circuits: Logic Design for an Emerging Technology. In International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2016. PDF
  91. R. Wille, N. Quetschlich, Y. Inoue, N. Yasuda, and S. Minato. Using πDDs for Nearest Neighbor Optimization of Quantum Circuits. In Conference on Reversible Computation, pages 181-196, 2016. PDF
  92. R. Wille, A. Lye, and P. Niemann. Checking Reversibility of Boolean Functions. In Conference on Reversible Computation, pages 322-337, 2016. PDF
  93. R. Wille, O. Keszocze, L. Othmer, M.K. Thomsen, and R. Drechsler. Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs. In Conference on Reversible Computation, pages 160-166, 2016.
  94. A. Paler. Circular CNOT Circuits: Definition, Analysis and Application to Fault-Tolerant Quantum Circuits. In Conference on Reversible Computation, pages 199-212, 2016. PDF
  95. A. Grimmer, F. Angerer, H. Prähofer, and P. Grünbaucher. Supporting Program Analysis for Non-Mainstream Languages: Experiences and Lessons Learned. In Software Analysis, Evolution, and Reengineering, 2016.
  96. J. Clemens, R. Wille, and K. Schill. Towards the exploitation of formal methods for information fusion. In Multisensor, Multisource Information Fusion: Architectures, Algorithms, and Applications, 2016. PDF
  97. F. Hilken, P. Niemann, M. Gogolla, and R. Wille. Towards a Catalog of Structural and Behavioral Verification Tasks for UML/OCL Models. In Modellierung, pages 117-124, 2016. PDF
  98. P. Niemann, R. Datta, and R. Wille. Logic Synthesis for Quantum State Generation. In International Symposium on Multiple-Valued Logic (ISMVL), pages 247-252, 2016. PDF
  99. Md. M. Rahman, G. W. Dueck, A. Chattopadhyay, and R. Wille. Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), pages 144-149, 2016. PDF
  100. L. Biswal, C. Bandyopadhyay, A. Chattopadhyay, R. Wille, R. Drechsler, and H. Rahaman. Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation. In International Symposium on Multiple- Valued Logic (ISMVL), pages 156-161, 2016. PDF
  101. Z. Al-Wardi, R. Wille, and R. Drechsler. Re-writing HDL Descriptions for Line-aware Synthesis of Reversible Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), pages 31-36, 2016. PDF
  102. N. Przigoda, G. W. Dueck, R. Wille, and R. Drechsler. Fault Detection in Parity Preserving Reversible Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), pages 44-49, 2016.
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  103. L. Amaru, P.-E. Gaillardon, R. Wille, and G. De Micheli. Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking. In Design, Automation and Test in Europe (DATE), pages 175-180, 2016. Acceptance rate: 34%. PDF
  104. R. Wille, O. Keszocze, S. Hillmich, M. Walter, and A. Garcia-Ortiz. Synthesis of Approximate Coders for On-chip Interconnects Using Reversible Logic. In Design, Automation and Test in Europe (DATE), pages 1140-1143, 2016. Acceptance rate: 34%. PDF
  105. R. Wille, O. Keszocze, M. Walter, P. Rohrs, A. Chattopadhyay, and R. Drechsler. Look-ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits. In Asia and South Pacific Design Automation Conference (ASP-DAC), pages 292-297, 2016. Acceptance rate: 34%. PDF
  106. L. Biswal, C. Bandyopadhyay, R. Wille, R. Drechsler, and H. Rahaman. Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library. In International Conference on VLSI Design (VLSI Design), pages 573-574, 2016. Acceptance rate: 33%.
  107. R. Drechsler and R. Wille. Reversible Computation: An Alternative Computation Paradigm for Low Power Applications. In International Green and Sustainable Computing Conference (IGSC), 2015. Invited paper PDF
  108. P. Niemann, F. Hilken, M. Gogolla, and R. Wille. Extracting Frame Conditions from Operation Contracts. In International Conference on Model Driven Engineering Languages and Systems (MODELS), pages 266-275, 2015. Acceptance rate: 26%. PDF
  109. N. Przigoda, C. Hilken, R. Wille, J. Peleska, and R. Drechsler. Checking Concurrent Behavior inUML/OCL Models. In International Conference on Model Driven Engineering Languages and Systems (MODELS), 2015. Acceptance rate: 26%. PDF
  110. O. Keszocze, R. Wille, K. Chakrabarty, and R. Drechsler. A General and Exact Routing Methodology for Digital Microfluidic Biochips. In International Conference on Computer Aided Design (ICCAD), 2015. Acceptance rate: 35%. PDF
  111. N. Przigoda, R. Wille, and R. Drechsler. Leveraging the Analysis for Invariant Independence in Formal System Models. In Euromicro Conference on Digital System Design (DSD), pages 359-366, 2015. PDF
  112. N. Przigoda, J. Stoppe, J. Seiter, R. Wille, and R. Drechsler. Verification-driven Design Across Abstraction Levels - A Case Study. In Euromicro Conference on Digital System Design (DSD), 375-382, 2015. PDF
  113. R. Drechsler, M. Fränzle, and R. Wille. Envisioning Self-Verification of Electronic Systems. In International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015. PDF
  114. P. Niemann, S. Basu, A. Chakrabarti, N. K. Jha, and R. Wille. Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions. In Conference on Reversible Computation (RC), 2015. PDF
  115. Z. Al-Wardi, R. Wille, and R. Drechsler. Towards Line-aware Realizations of Expressions for HDL-based Synthesis of Reversible Circuits. In Conference on Reversible Computation (RC), 2015. PDF
  116. A. Kole, K. Datta, I. Sengupta, and R. Wille. Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits. In Conference on Reversible Computation (RC), 2015. PDF
  117. F. Hilken, P. Niemann, M. Gogolla, and R. Wille. From UML/OCL to Base Models: Transformation Concepts for Generic Validation and Verification. In International Conference on Model Transformation (ICMT), 2015. PDF
  118. J. Peters, R. Wille, N. Przigoda, U. Kühne, and R. Drechsler. A Generic Representation of CCSL Time Constraints for UML/MARTE Models. In Design Automation Conference (DAC), pages 122:1-122:6, 2015. Acceptance rate: 20%. PDF
  119. N. Przigoda, R. Wille, and Rolf Drechsler. Contradiction Analysis for Inconsistent Formal Models. In International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 171-176,2015. PDF
  120. A. Deb, R. Wille, R. Drechsler, and D. Das. An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization. In International Symposium on Multiple-Valued Logic (ISMVL), 2015. PDF
  121. A. Allahyari-Abhari, R. Wille, and R. Drechsler. An Examination of the NCV-v1 Quantum Library Based on Minimal Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), 2015. PDF
  122. C. Hilken, J. Peleska, and R. Wille. A Unified Formulation of Behavioral Semantics for SysML Models. In Int’l Conf. on Model-Driven Engineering and Software Development, 2015. PDF
  123. P. Niemann, F. Hilken, M. Gogolla, and R. Wille. Assisted Generation of Frame Conditions for Formal Models. In Design, Automation and Test in Europe (DATE), pages 309-312, 2015. Acceptance rate: 32%. PDF
  124. J. Stoppe, R. Wille, and R. Drechsler. Automated Feature Localization for Dynamically Generated SystemC Designs. In Design, Automation and Test in Europe (DATE), pages 277-280, 2015. Acceptance rate: 32%. PDF
  125. E. Schönborn, K. Datta, R. Wille, I. Sengupta, H. Rahaman, and R. Drechsler. BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits. In International Conference on VLSI Design (VLSI Design), pages 435-440, 2015. PDF
  126. R. Wille, O. Keszocze, C. Hopfmuller, and R. Drechsler. Reverse BDD-based Synthesis for Splitter-free Optical Circuits. In Asia and South Pacific Design Automation Conference (ASP-DAC), pages 172-177, 2015. Acceptance rate: 34%. PDF
  127. A. Lye, R. Wille, and R. Drechsler. Determining the Minimal Number of SWAP Gates for Multi-dimensional Nearest Neighbor Quantum Circuits. In Asia and South Pacific Design Automation Conference (ASP-DAC), pages 178-183, 2015. Acceptance rate: 34%. PDF
  128. J. Seiter, R. Wille, U. Kühne, and R. Drechsler. Automatic Refinement Checking for Formal System Models. In Forum on Specification and Design Languages (FDL), pages 1-8, 2014. Best Paper Award Candidate. PDF
  129. C. Hilken, J. Seiter, R. Wille, U. Kühne, and R. Drechsler. Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts. In Forum on Specification and Design Languages (FDL), pages 1-7, 2014. PDF
  130. O. Keszocze, B. Keiner, M. Richter, G Antpöhler, and R. Wille. (Semi-)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications. In Special Session at the Forum on Specification and Design Languages (FDL), 2014. PDF
  131. O. Keszöcze, R. Wille, and R. Drechsler. Exact Routing for Digital Microfluidic Biochips with Temporary Blockages. In International Conference on Computer Aided Design (ICCAD), pages 599-606, 2014. Acceptance rate: 25%. PDF
  132. S. Yang, R. Wille, and R. Drechsler. Improving Coverage of Simulation-based Verification by Dedicated Stimuli Generation. In Euromicro Conference on Digital System Design (DSD), pages 599-606, 2014. PDF
  133. S. Yang, R. Wille, and R. Drechsler. Determining Cases of Scenarios to Improve Coverage in Simulation-based Verication. In Symposium on Integrated Circuits and System Design (SBCCI), 2014. PDF
  134. J. Stoppe, R. Wille, and R. Drechsler. Validating SystemC Implementations Against Their Formal Specifications. In Symposium on Integrated Circuits and System Design (SBCCI), 2014. PDF
  135. F. Hilken, P. Niemann, M. Gogolla, and R. Wille. Filmstripping and Unrolling: A Comparison of Verification Approaches for UML and OCL Behavioral Models. In International Conference on Tests & Proofs (TAP), pages 99-116, 2014. PDF
  136. J. Peters, R. Wille, and R. Drechsler. Generating SystemC Implementations for Clock Constraints specified in UML/MARTE CCSL. In International Conference on Engineering of Complex Computer Systems (ICECCS), pages 116-125, 2014. Acceptance rate: 27%. PDF
  137. P. Niemann, R. Wille, and R. Drechsler. Equivalence Checking in Multi-level Quantum Systems. In Conference on Reversible Computation, pages 201-215, 2014. PDF
  138. R. Wille, J. Stoppe, E. Schönborn, K. Datta, and R. Drechsler. RevVis: Visualization of Structures and Properties in Reversible Circuits. In Conference on Reversible Computation, pages 111-124, 2014. PDF
  139. E. Schönborn, K. Datta, R. Wille, I. Sengupta, H. Rahaman, and R. Drechsler. Optimizing DD-based Synthesis of Reversible Circuits using Negative Control Lines. In International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 129-134, 2014. PDF
  140. O. Keszöcze, R. Wille, T.-Y. Ho, and R. Drechsler. Exact One-pass Synthesis of Digital Microfluidic Biochips. In Design Automation Conference (DAC), 2014. Acceptance rate: 22%. PDF
  141. R. Wille, A. Lye, and R. Drechsler. Optimal SWAP Gate Insertion for Nearest Neighbor Quantum Circuits. In Asia and South Pacific Design Automation Conference (ASP-DAC), pages 489-494, 2014. Acceptance rate: 31%. PDF
  142. P. Niemann, R. Wille, and R. Drechsler. Efficient Synthesis of Quantum Circuits Implementing Clifford Group Operations. In Asia and South Pacific Design Automation Conference (ASP-DAC), pages 483-498, 2014. Acceptance rate: 31%, Best Paper Award Candidate. PDF
  143. S. Eggersglüß, R. Wille, and Rolf Drechsler. Improved SAT-based ATPG: More Constraints, Better Compaction. In International Conference on Computer Aided Design (ICCAD), pages 85-90, 2013. Acceptance rate: 26%, Received Best Paper Award. PDF
  144. R. Wille, N. Przigoda, and Rolf Drechsler. A Compact and Efficient SAT Encoding for Quantum Circuits. In IEEE AFRICON, 2013. PDF
  145. R. Wille, S. Stelter, and R. Drechsler. Exploiting Reversibility in the Complete Simulation of Reversible Circuits. In IEEE AFRICON, 2013. PDF
  146. J. Stoppe, R. Wille, and R. Drechsler. Cone of Influence Analysis at the Electronic System Level Using Machine Learning. In Euromicro Conference on Digital System Design (DSD), pages 582-587, 2013. PDF
  147. S. Yang, R. Wille, D. Große, and R. Drechsler. Minimal Stimuli Generation in Simulation-based Verification. In Euromicro Conference on Digital System Design (DSD), pages 439-444, 2013. PDF
  148. R. Wille and R. Drechsler. The SyReC Hardware Description Language: Enabling Scalable Synthesis of Reversible Circuits. In Midwest Symposium on Circuits and Systems, 2013.
  149. J. Stoppe, R. Wille, and R. Drechsler. Data Extraction from SystemC Designs using Debug Symbols and the SystemC API. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 26-31, 2013. PDF
  150. P. Niemann, R. Wille, and R. Drechsler. On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure. In Conference on Reversible Computation, 2013. PDF
  151. N. Abdessaied, R. Wille, M. Soeken, and R. Drechsler. Reducing the Depth of Quantum Circuits Using Additional Lines. In Conference on Reversible Computation, 2013. PDF
  152. K. Datta, G. Rathi, R. Wille, I. Sengupta, H. Rahaman, and R. Drechsler. Exploiting Negative Control Lines in the Optimization of Reversible Circuits. In Conference on Reversible Computation, 2013. PDF
  153. A. Deb, D. Kumar Das, H. Rahaman, B. B. Bhattacharya, R. Wille, and R. Drechsler. Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure. In Conference on Reversible Computation, 2013. PDF
  154. R. Wille, H. Zhang, and R. Drechsler. Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), 2013. PDF
  155. N., Abdessaied, M. Soeken, R. Wille, and R. Drechsler. Exact Template Matching Using Boolean Satisfiability. In International Symposium on Multiple-Valued Logic (ISMVL), 2013. PDF
  156. R. Wille, M. Gogolla, M. Soeken, M. Kuhlmann, and R. Drechsler. Towards a Generic Verification Methodology for System Models. In Design, Automation and Test in Europe (DATE), 2013. Acceptance rate: 36%. PDF
  157. J. Seiter, R. Wille, M. Soeken, and R. Drechsler. Determining Relevant Model Elements for the Verification of UML/OCL Specifications. In Design, Automation and Test in Europe (DATE), 2013. Acceptance rate: 36%. PDF
  158. R. Wille, M. Soeken, C. Otterstedt, and R. Drechsler. Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2013. Acceptance rate: 31%. PDF
  159. R. Drechsler, M. Soeken, and R. Wille. Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems. In International Design & Test Symposium (IDT), 2012. Invited Paper. PDF
  160. R. Drechsler and R. Wille. Synthesis of Reversible Circuits Using Decision Diagrams. In International Symposium on Electronic System Design (ISED), 2012. Invited Paper. PDF
  161. R. Drechsler, M. Diepenbeck, D. Große, U. Kühne, H. M. Le, J. Seiter, M. Soeken, and R. Wille. Completeness-Driven Development. In International Conference on Graph Transformations (ICGT), 2012. Invited Paper. PDF
  162. R. Drechsler, M. Soeken, and R. Wille. Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing. In Forum on Specification and Design Languages (FDL), 2012. Invited Paper. PDF
  163. R. Wille, M. Soeken, E. Schönborn, and R. Drechsler. Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2012. PDF
  164. S. Yang, R. Wille, D. Große, and R. Drechsler. Coverage-driven Stimuli Generation. In Euromicro Conference on Digital System Design (DSD), 2012. PDF
  165. R. Drechsler and R. Wille. Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology. In International Symposium on VLSI Design and Test (VDAT), 2012. Invited Paper. PDF
  166. M. Soeken, R. Wille, and R. Drechsler. Assisted Behavior Driven Development Using Natural Language Processing. In International Conference on Objects, Models, Components, Patterns (TOOLS), 2012. Acceptance rate: 31%. PDF
  167. Z. Sasanian, R. Wille, and D. M. Miller. Realizing Reversible Circuits Using a New Class of Quantum Gates. In Design Automation Conference (DAC), 2012. Acceptance rate: 22%. PDF
  168. M. Soeken, Z. Sasanian, R. Wille, D. M. Miller, and Rolf Drechsler. Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), 2012. PDF
  169. M. Soeken, R. Wille, C. Otterstedt, and R. Drechsler. A Synthesis Flow for Sequential Reversible Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), 2012. PDF
  170. R. Wille, M. Soeken, N. Przigoda, and R. Drechsler. Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines. In International Symposium on Multiple-Valued Logic (ISMVL), 2012. PDF
  171. R. Wille, R. Drechsler, C. Oswald, and A. Garcia-Ortiz. Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis. In Design, Automation and Test in Europe (DATE), pages 1036-1041, 2012. Acceptance rate: 27%. PDF
  172. R. Wille, M. Soeken, and R. Drechsler. Debugging of Inconsistent UML/OCL Models. In Design, Automation and Test in Europe (DATE), pages 1078-1083, 2012. Acceptance rate: 27%. PDF
  173. M. Soeken, R. Wille, and R. Drechsler. Eliminating Invariants in UML/OCL Models. In Design, Automation and Test in Europe (DATE), pages 1142-1145, 2012. Acceptance rate: 27%. PDF
  174. M. Soeken, R. Wille, C. Hilken, N. Przigoda, and R. Drechsler. Synthesis of Reversible Circuits with Minimal Lines for Large Functions. In Asia and South Pacific Design Automation Conference (ASP-DAC), pages 85-92, 2012. Acceptance rate: 34%. PDF
  175. H. Zhang, R. Wille, and Rolf Drechsler. Improved Fault Diagnosis for Reversible Circuits. In Asian Test Symposium (ATS), pages 207-212, 2011. PDF
  176. S. Offermann, R. Wille, and R. Drechsler. Efficient Realization of Control Logic in Reversible Circuits. In Forum on Specification and Design Languages (FDL), 2011. PDF
  177. H. Zhang, S. Frehse, R. Wille, and R. Drechsler. Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability. In IEEE AFRICON, 2011. PDF
  178. R. Wille, A. Sülflow, and R. Drechsler. VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification. In International Conference on Modeling, Simulation and Visualization Methods (MSV), pages 36-39, 2011. PDF
  179. R. Wille, H. Zhang, and R. Drechsler. ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2011. PDF
  180. M. Soeken, R. Wille, and R. Drechsler. Encoding OCL Data Types for SAT-based Verification of UML/OCL Models. In International Conference on Tests & Proofs (TAP), pages 152-170, 2011. PDF
  181. R. Wille, M. Soeken, D. Große, E. Schönborn, and R. Drechsler. Designing a RISC CPU in Reversible Logic. In International Symposium on Multiple-Valued Logic (ISMVL), pages 170-175, 2011. PDF
  182. R. Drechsler and R. Wille. From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), pages 78-85, 2011. Invited Paper. PDF
  183. D. M. Miller, R. Wille, and Z. Sasanian. Elementary Quantum Gate Realizations for Multiple-Control Toffolli Gates. In International Symposium on Multiple-Valued Logic (ISMVL), pages 288-293, 2011. PDF
  184. R. Wille. An Introduction to Reversible Circuit Design. In Saudi International Electronics, Communications and Photonics Conference (SIECPC), 2011. Invited Paper. PDF
  185. M. Soeken, R. Wille, and R. Drechsler. Verifying Dynamic Aspects of UML Models. In Design, Automation and Test in Europe (DATE), 2011. Acceptance rate: 34%. PDF
  186. R. Wille, O. Keszöcze, and R. Drechsler. Determining the Minimal Number of Lines for Large Reversible Circuits. In Design, Automation and Test in Europe (DATE), 2011. Acceptance rate: 34%. PDF
  187. R. Wille, S. Offermann, and R. Drechsler. SyReC: A Programming Language for Synthesis of Reversible Circuits. In Forum on Specification and Design Languages (FDL), pages 184-189, 2010. Received Best Paper Award. PDF
  188. H.-J. Kreowski, S. Kuske, and R. Wille. Graph Transformation Units Guided by a SAT Solver. In International Conference on Graph Transformations (ICGT), pages 27-42, 2010. PDF
  189. R. Wille, M. Soeken, and R. Drechsler. Reducing the Number of Lines in Reversible Circuits. In Design Automation Conference (DAC), pages 647-652, 2010. Acceptance rate: 24%. PDF
  190. S. Offermann, R. Wille, G. W. Dueck, and R. Drechsler. Synthesizing Multiplier in Reversible Logic. In International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 335-340, 2010. PDF
  191. M. Soeken, R. Wille, G. W. Dueck, and R. Drechsler. Window Optimization of Reversible and Quantum Circuits. In International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 431-435, 2010. PDF
  192. J. C. Jung, S. Frehse, R. Wille, and R. Drechsler. Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic. In Great Lakes Symposium on VLSI (GLVLSI), pages 465-470, 2010. PDF
  193. M. Soeken, R. Wille, M. Kuhlmann, M. Gogolla, and R. Drechsler. Verifying UML/OCL Models Using Boolean Satisfiability. In Design, Automation and Test in Europe (DATE), pages 1341-1344, 2010. Acceptance rate: 30%. PDF
  194. S. Frehse, R. Wille, and R. Drechsler. Efficient Simulation-based Debugging of Reversible Logic. In International Symposium on Multiple-Valued Logic (ISMVL), pages 156-161, 2010. PDF
  195. D. M. Miller, R. Wille, and R. Drechsler. Reducing Reversible Circuit Cost by Adding Lines. In International Symposium on Multiple-Valued Logic (ISMVL), pages 217-222, 2010. PDF
  196. R. Wille, D. Große, F. Haedicke, and Rolf Drechsler. SMT-based Stimuli Generation in the SystemC Verification Library. In Forum on Specification and Design Languages (FDL), 2009. PDF
  197. D.M. Miller, R. Wille, and G.W. Dueck. Synthesizing Reversible Circuits for Irreversible Functions. In Euromicro Conference on Digital System Design (DSD), pages 749-756, 2009. PDF
  198. R. Wille and Rolf Drechsler. BDD-based Synthesis of Reversible Logic for Large Functions. In Design Automation Conference (DAC), pages 270-275, 2009. Acceptance rate: 22%. PDF
  199. D. Große, R. Wille, U. Kühne, and Rolf Drechsler. Contradictory Antecedent Debugging in Bounded Model Checking. In Great Lakes Symposium on VLSI (GLVLSI), pages 173-176, 2009. PDF
  200. A. Sülflow, R. Wille, G. Fey, and Rolf Drechsler. Evaluation of Cardinality Constraints on SMT-based Debugging. In International Symposium on Multiple-Valued Logic (ISMVL), pages 298-303, 2009. PDF
  201. R. Wille, D. Große, D.M. Miller, and Rolf Drechsler. Equivalence Checking of Reversible Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), pages 324-330, 2009. PDF
  202. R. Wille, D. Große, S. Frehse, G.W. Dueck, and Rolf Drechsler. Debugging of Toffoli Networks. In Design, Automation and Test in Europe (DATE), pages 1284-1289, 2009. Acceptance rate: 23%. PDF
  203. R. Wille, D. Große, G.W. Dueck, and R. Drechsler. Reversible Logic Synthesis with Output Permutation. In International Conference on VLSI Design (VLSI Design), pages 189-194, 2009. Acceptance rate: 26%. PDF
  204. R. Wille, G. Fey, M. Messing, G. Angst, L. Linhard, and R. Drechsler. Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. In Euromicro Conference on Digital System Design (DSD), pages 411-416, 2008. PDF
  205. D. Große, R. Wille, R. Siegmund, and R. Drechsler. Contradiction Analysis for Constraint-based Random Simulation. In Forum on Specification and Design Languages (FDL), pages 411-416, 2008. PDF
  206. R. Wille, D. Große, M. Soeken, and R. Drechsler. Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 411-416, 2008. Acceptance rate: 28%. PDF
  207. R. Wille, D. Große, L. Teuber, G.W. Dueck, and R. Drechsler. RevLib: An Online Resource for Reversible Functions and Reversible Circuits. In International Symposium on Multiple-Valued Logic (ISMVL), pages 220-225, 2008. RevLib is available at http://www.revlib.org. PDF
  208. D. Große, R. Wille, G.W. Dueck, and R. Drechsler. Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don’t Cares. In International Symposium on Multiple-Valued Logic (ISMVL), pages 214-219, 2008. Received IEEE Young Researchers Award. PDF
  209. R. Wille, H. M. Le, G.W. Dueck, and D. Große. Quantified Synthesis of Reversible Logic. In Design, Automation and Test in Europe (DATE), pages 1015-1020, 2008. Acceptance rate: 24%. PDF
  210. R. Wille and D. Große. Fast Exact Toffoli Network Synthesis of Reversible Logic. In International Conference on Computer Aided Design (ICCAD), pages 60-64, 2007. Acceptance rate: 27%. PDF
  211. R. Wille, G. Fey, D. Große, S. Eggersglüß, and R. Drechsler. SWORD: A SAT like Prover using Word Level Information. In IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC), pages 88-93, 2007. PDF

Peer-reviewed Workshops

  1. S. Hillmich, L. Burgholzer, and R. Wille. Efficient and Correct Compilation of Quantum Circuits. In International Workshop on Quantum Compilation (IWQC), 2019.
  2. L. Servadei, E. Mosca J.-H. Lee, J. Yang, V. Esen, R. Wille, and W. Ecker. Combining Evolutionary Algorithms and Deep Learning for Hardware/Software Interface Optimization. In Workshop on Machine Learning for CAD (MLCAD), 2019.
  3. L. Servadei, J. Yang, E. Zennaro, K. Devarajegowda, W. Ecker, and R. Wille. Methods of Statistical Analysis and Machine Learning for the Evaluation of Generated Hardware and Firmware Design. In International Workshop on Combinations of Intelligent Methods and Applications, 2019.
  4. M. Walter, R. Wille, F. Sill Torres, D. Große, and R. Drechsler. fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits. In International Workshop on Logic Synthesis (IWLS), 2019.
  5. M. Hamidovic, U. Marta, A. Grimmer, G. Fink, R. Wille, H. Bridle, A. Springer, and W. Haselmayr. First Practical Realization of Switching in Microfluidic Networks. In Workshop on Molecular Communications (MolCom), 2018. PDF
  6. L. Servadei, E. Zennaro, K. Devarajegowda, W. Ecker, and R. Wille. Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning. In International Workshop on Combinations of Intelligent Methods and Applications, 2018. PDF
  7. A. Zulehner and R. Wille. Compiling Quantum Circuits to the IBM QX Architectures. In International Workshop on Quantum Compilation (IWQC), 2018.
  8. P. Niemann, R. Wille, and R. Drechsler. Optimizing “Ts” in the Synthesis of Clifford+T Quantum Circuits. In International Workshop on Quantum Compilation (IWQC), 2018.
  9. M. Hamidovic, W. Haselmayr, A. Grimmer, and R. Wille. Towards Droplet on Demand for Microfluidic Networks. In Workshop on Molecular Communications (MolCom), 2018. PDF
  10. A. Grimmer, W. Haselmayr, A. Springer, R. Wille. Verifikation von Networked Labs-on-Chip Architekturen. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2017.
  11. N. Przigoda, F. Hilken, J. Peters, R. Wille, M. Gogolla, and R. Drechsler. Integrating an SMT-based Model Finder into USE. In Model-Driven Engineering, Verification, And Validation (MoDeVVa), 2016.
  12. R. Wille. Reversible Logic: Whats next? In International Workshop on Post-Binary ULSI Systems (ULSIWS), 2016. Invited Paper.
  13. Z. Alwardi, R. Wille, and R. Drechsler. Optimized Realizations of Expressions for HDL-based Synthesis of Reversible Logic Circuits. In International Workshop on Post-Binary ULSI Systems (ULSIWS), 2016.
  14. P. Niemann, F. Hilken, M. Gogolla, and R. Wille. Extraktion von Frame Conditions aus Operation Contracts. In Software Engineering (SE), 2016.
  15. J. Stoppe, O. Keszocze, R. Wille, and R. Drechsler. BioViz: An Interactive Visualization Engine for Microfluidic Biochips. In Workshop on Design Automation for Understanding Hardware Designs (DUHDE), 2016.
  16. A. Deb, R. Wille, O. Keszocze, S. Hillmich, and R. Drechsler. Synthesis of Optical Circuits with Contradictory Optimization Objectives. In International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS), 2016.
  17. N. Przigoda, J. Peters, M. Soeken, R. Wille, and R. Drechsler. Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses. In Model-Driven Engineering, Verification, And Validation (MoDeVVa), 2015.
  18. R. Wille. Verification and Debugging of UML/OCL Models. In International Workshop on Constraints in Formal Verification (CFV), 2015.
  19. E. Schönborn, R. Wille, and R. Drechsler. Quo Vadis, Reversible Circuit Design? Towards Scaling Design and Synthesis of Reversible Circuits. In International Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM), 2015.
  20. N. Przigoda, R. Wille, and R. Drechsler. Verbesserung der Fehlersuche in inkonsistenten formalen Modellen. In ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2015.
  21. F. Hilken, P. Niemann, R. Wille, and M. Gogolla. Towards a Base Model for UML and OCL Verification. In Model-Driven Engineering, Verification, and Validation (MoDeVVa), 2014.
  22. J. Stoppe, M. Michael, M. Soeken, R. Wille, and R. Drechsler. Towards a Multi-dimensional and Dynamic Visualization for ESL Designs. In Design Automation for Understanding Hardware Designs, 2014.
  23. R. Drechsler, H. M. Le, M. Soeken, and R. Wille. Law-based Verification for Complex Swarm Systems. In International Workshop on the Swarm at the Edge of the Cloud, 2013.
  24. R. Drechsler, M. Diepenbeck, S. Eggersglüß, and R. Wille. PASSAT 2.0: A Multi-Functional SAT-based Testing Framework. In Latin-American Test Workshop (LATW), 2013. Invited Paper.
  25. M. Soeken, R. Wille, E. Kuksa, and R. Drechsler. Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen. In ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013.
  26. M. Soeken, H. Riener, R. Wille, G. Fey, and R. Drechsler. Verification of Embedded Systems Using Modeling and Implementation Languages. In International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs), 2012.
  27. S. Eggersglüß, M. Diepenbeck, R. Wille, and R. Drechsler. Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints. In Workshop on RTL and High Level Testing (WRTLT), 2012.
  28. M. Soeken, R. Wille, L. Tague, D. M. Miller, and R. Drechsler. Towards Embedding of Large Functions for Reversible Logic. In International Workshop on Boolean Problems (IWSBP), 2012.
  29. M. Soeken, R. Wille, S.-I. Minato, and R. Drechsler. Using πDDs in the Design for Reversible Circuits. In Workshop on Reversible Computation, 2012.
  30. J. Seiter, M. Soeken, R. Wille, and R. Drechsler. Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams. In Workshop on Reversible Computation, 2012.
  31. M. Soeken, R. Wille, and Rolf Drechsler. Towards Automatic Determination of Problem Bounds for Object Instantiation in Static Model Verification. In Model-Driven Engineering, Verification, And Validation (MoDeVVa), 2011.
  32. M. Soeken, R. Wille, C. Hilken, N. Przigoda, and R. Drechsler. Synthesis of Reversible Circuits with Minimal Lines for Large Functions. In Workshop on Reversible Computation, pages 59-70, 2011.
  33. M. Soeken, S. Frehse, R. Wille, and R. Drechsler. Customized Design Flows for Reversible Circuits Using RevKit. In Workshop on Reversible Computation, pages 91-96, 2011.
  34. R. Drechsler, A. Finder, and R. Wille. Improving ESOP-based Synthesis of Reversible Logic Using Evolutionary Algorithms. In European Workshop on Hardware Optimization Techniques (Evo-HOT), pages 151-161, 2011.
  35. R. Wille, M. Soeken, D. Große, E. Schönborn, and R. Drechsler. Designing a RISC CPU in Reversible Logic. In ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011.
  36. H. Zhang, R. Wille, and R. Drechsler. SAT-based ATPG for Reversible Circuits. In International Design & Test Workshop (IDT), pages 149-154, 2010.
  37. M. Soeken, R. Wille, and R. Drechsler. Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition. In International Design & Test Workshop (IDT).
  38. M. Soeken, S. Frehse, R. Wille, and R. Drechsler. RevKit: A Toolkit for Reversible Circuit Design. In Workshop on Reversible Computation, pages 69-72, 2010.
  39. R. Wille, S. Offermann, and R. Drechsler. SyReC: A Programming Language for Synthesis of Reversible Circuits. In International Workshop on Logic Synthesis (IWLS), 2010.
  40. R. Wille, A. Sülflow, C. Genz, and R. Drechsler. VisSAT: Visualization of SAT Solver Internals. In University Booth at Design, Automation and Test in Europe, 2010.
  41. R. Wille, S. Offermann, and R. Drechsler. SyReC: A Programming Language for Synthesis of Reversible Circuits. In ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010.
  42. M. Soeken, R. Wille, M. Kuhlmann, M. Gogolla, and R. Drechsler. Verifying UML/OCL Models Using Boolean Satisfiability. In ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 57-66, 2010.
  43. D. M. Miller, R. Wille, and R. Drechsler. Reducing Reversible Circuit Cost by Adding Lines. In International Workshop on Logic Synthesis (IWLS), pages 243-248, 2009.
  44. R. Wille, M. Saeedi, and R. Drechsler. Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost. In International Workshop on Logic Synthesis (IWLS), pages 43-49, 2009.
  45. R. Wille and R. Drechsler. Synthesizing Reversible Logic: An Overview. In International Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM), 2009.
  46. D.M. Miller, G.W. Dueck, and R. Wille. Synthesising Reversible Circuits from Irreversible Specifications using Reed-Muller Spectral Techniques. In International Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM), 2009.
  47. A. Sülflow, R. Wille, C. Genz, G. Fey, and R. Drechsler. FormED: A Formal Environment for Debugging. In University Booth at Design, Automation and Test in Europe, 2009.
  48. R. Wille and R. Drechsler. Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic. In Workshop on Reversible Computation, 2009.
  49. R. Wille, D. Große, D.M. Miller, and R. Drechsler. Equivalence Checking of Reversible Circuits. In ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009.
  50. R. Wille, D. Große, G. W. Dueck, and R. Drechsler. Reversible Logic Synthesis with Output Permutation. In International Workshop on Boolean Problems (IWSBP), 2008.
  51. D. Große, R. Wille, R. Siegmund, and R. Drechsler. Contradiction Analysis for Constraint-based Random Simulation. In Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS), pages 25-30, 2008.
  52. D. Große, R. Wille, U. Kühne, and R. Drechsler. Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking. In ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 169-178, 2008.
  53. A. Sülflow, U. Kühne, R. Wille, D. Große, and R. Drechsler. Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits. In Workshop on RTL and High Level Testing (WRTLT), pages 31-36, 2007.
  54. D. Tille, R. Wille, and R. Drechsler. Parallelisierung von SAT-basierter Testmustergenerierung. In Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS), 2007.
  55. R. Wille, G. Fey, and R. Drechsler. Building Free Binary Decision Diagrams Using SAT Solvers. In International Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM), 2007.
  56. G. Fey, D. Große, S. Eggersglüß, R. Wille, and R. Drechsler. Formal Verification on the Word Level using SAT-like Proof Techniques. In ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 165-173, 2007.

Miscellaneous

  1. Alwin Zulehner and Robert Wille. How can we work with quantum computers today? Science Journal for Teens, 2019. PDF
  2. R. Wille. Design of Circuits and Systems: Today and Tomorrow. Universität Bremen, 2014.
  3. Z. Sasanian, R. Wille, and D. M. Miller. Clarification on the Mapping of Reversible Circuits to the NCV-v1 Library. arXiv:1309.1419, 2013.
  4. R. Wille, J. Christoph Jung, A. Sülflow, and R. Drechsler. SWORD - Module-based SAT Solving. In Bernd Becker, Valeria Bertacoo, Rolf Drechsler, and Masahiro Fujita, editors, Algorithms and Applications for Next Generation SAT Solvers, number 09461 in Dagstuhl Seminar Proceedings. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany, 2010. Invited Paper.
  5. R. Wille. Towards a Design Flow for Reversible Logic. Dissertation, University of Bremen, 2009.
  6. R. Wille. Towards a Design Flow for Reversible Logic. ACM SIGDA Ph.D. Forum at DAC, 2009. Acceptance rate: 31%.
  7. J. C. Jung, A. Sülflow, R. Wille, and R. Drechsler. SWORD v1.0. Satisfiability Modulo Theories Competition, 2009.
  8. R. Wille, A. Sülflow, and R. Drechsler. SWORD v0.2 - Module-based SAT Solving. Satisfiability Modulo Theories Competition, 2008.
  9. R. Wille. Erstellung von Free Binary Decision Diagrams mit SAT Beweisern. Diploma thesis, University of Bremen, 2006.